6th Workshop on Dynamic Resources in HPC (DynResHPC27)
Status: under review. This workshop proposal is still under review by the ISC workshop committee. The rest of this page: including dates, program details, and submission information; may change after that decision.
About
The 6th Workshop on Dynamic Resources in HPC (DynResHPC) is a full-day workshop at ISC 2027.
Dynamic resource management on large-scale HPC platforms is a key component of several past, currently running, and future projects. It poses highly interdisciplinary challenges concerning, among others, the applications that support dynamic resources, extending dynamic resource provisioning to the full system stack, I/O adaptable systems, and I/O scheduling, among others.
This workshop brings together research across the full-stack: runtime adaptive applications that can modify their allocation, system architecture, resource managers, runtime systems, programming models, I/O and storage, and tools. Consequently, computation, communication, and I/O can be coordinated, platforms better utilized, and application makespan reduced. It is organized in connection with the DynResHPC consortium.
Topics of interest
This workshop is planned to be an amplifier of collaborations around these ideas and covers the following topics (but is not limited to):
- System and system architecture considerations in designing architectures that use dynamic resources
- Emerging software designs to achieve dynamic resource management in high-performance computing
- High-level parallel programming models and programmability techniques to improve applications’ dynamic resource utilization
- Runtime techniques to provide dynamic resource execution models for computation, communication, and I/O
- Resource management frameworks and interfaces supporting dynamic resource management
- Computing and I/O scheduling algorithms providing and/or exploiting static or dynamic resources
- Use of AI and ML techniques to steer dynamic resources in systems and applications
- Ad-hoc storage systems and I/O scheduling techniques supporting dynamic resource provisioning in I/O
- Support for dynamic resource execution of applications in performance, debugging, and correctness tools
- Experiences and use cases applying dynamic resource management to HPC applications
- Experience adopting dynamic resource frameworks
- Performance monitoring and modelling in dynamic environments
Important dates
All deadlines are Anywhere on Earth (AoE).
- Abstract submission deadline: 22 February 2027
- Paper submission deadline: 1 March 2027
- Author notification: 2 April 2027
- Camera-ready papers: 23 April 2027
Submission and Publication
Papers must use the two-column LaTeX format with the FGCS templates provided for ISC workshops. All source files must be submitted.
Paper length (excluding references):
- Regular papers: 7–10 pages; up to +2 extra pages after review to address reviewer comments
- Short papers: 4–6 pages; up to +1 extra page after review to address reviewer comments
- Papers will be reviewed by at least 3 reviewers.
Publication:
- Papers must be submitted through the Linklings ISC submission portal.
- Accepted papers will be published in Future Generation Computer Systems (Elsevier) - with worldwide open access for four weeks.
Templates and guidelines:
- FGCS LaTeX templates (zip)
- FGCS LaTeX preview (PDF)
- Elsevier FGCS instructions for authors (workshop papers)
Authors must also follow Elsevier publishing ethics.
Agenda (full day)
Planned session outline (detailed timings and the number of talks will be set after paper acceptance and the ISC slot assignment):
- Opening
- Keynote (speaker to be confirmed)
- Technical paper sessions (accepted papers)
- Tutorial (speaker to be confirmed)
- Closing panel with discussion
Organizing committee
General chairs
- Dr. Iker Martín-Álvarez, Universitat Jaume I, Spain
- Dr. Sergio Iserte, Barcelona Supercomputing Center, Spain
- Dr. Martin Schreiber, Université Grenoble Alpes, France
Program chairs
- Dr. David E. Singh, Universidad Carlos III de Madrid, Spain
- Dominik Huber, Technical University of Munich, Germany
Publicity and web chair
- Dr. Iker Martín-Álvarez, Universitat Jaume I, Spain
Steering committee
- Prof. Martin Schulz, Technical University of Munich, Germany
- Prof. Antonio J. Peña, Barcelona Supercomputing Center, Spain
- Prof. Jesús Carretero, Universidad Carlos III de Madrid, Spain
- Prof. Sheikh Ghafoor, Tennessee Tech University, USA
Program committee
All members below are tentative; none have confirmed yet.
- Jean-Baptiste Besnard, ParaTools
- Pierre-François Dutot, Université Grenoble Alpes, France
- Paula Sánchez Checa, Universidad Carlos III de Madrid, Spain
- José I. Aliaga, Universitat Jaume I, Spain
- Ahmad Tarraf, Technische Universität Darmstadt, Germany
- Daniel Milroy, Lawrence Livermore National Laboratory, USA
- Rajat Bhattarai, Tennessee Tech University, USA
- Petter Sandås, Barcelona Supercomputing Center, Spain
- Sonja Happ, Par-Tec, Germany
Previous editions
- 1st workshop - 5–6 September 2022, Technical University of Munich, Germany
- 1st hackathon - 23–27 January 2023, Université Grenoble Alpes, France
- 2nd workshop/hackathon - 16–20 October 2023, Barcelona Supercomputing Center, Spain
- 3rd workshop - 26–27 August 2024, collocated with Euro-Par 2024, Universidad Carlos III de Madrid, Spain
- 4th workshop - 25 August 2025, collocated with Euro-Par 2025
- 5th workshop - 11–12 February 2026, Université Grenoble Alpes, France